Electroplating methods are commonly used in numerous applications such as depositing metal films including copper interconnects in semiconductor devices and forming magnetic layers in magnetic recording devices. Although magnetic layers in read and write heads may be deposited by a sputtering method, an electroplating process is usually preferred because the sputtering process produces a magnetic layer with large magnetocrystalline anisotropy and higher internal stress. Electroplating is capable of generating a magnetic layer with a smaller crystal grain size and a smoother surface that leads to a high magnetic flux density (BS) value and low coercive force (HC).
In an electroplating process, an electric current is passed through an electroplating cell comprised of a working electrode (cathode), counter electrode (anode), and an aqueous electrolyte solution of positive ions of the metals to be plated on a substrate in physical contact with the cathode. By applying a potential to the electrodes, an electrochemical process is initiated wherein cations migrate to the cathode and anions migrate to the anode. Metallic ions such as Fe+2, Co+2, and Ni+2 deposit on a substrate (cathode) to form an alloy that may be NiFe, CoFe, or CoNiFe, for example. The substrate typically has an uppermost seed layer on which a photoresist layer is patterned to provide openings over the seed layer that define the shape of the metal layer to be plated. Once the metal layer is deposited, the photoresist layer is removed. The magnetic layers which become a bottom pole layer and top pole layer in a write head can be formed in this manner.
During the manufacture of magnetic recording heads, the devices are typically built on an AlTiC wafer with a flat or notch along an edge of the wafer. The flat or notch may be used for orientation identification (in a plane with x-axis and y-axis dimensions) and is sometimes required for equipment such as exposure tools to process wafers. Unfortunately, the presence of a flat or notch can adversely produce poor within-wafer uniformity because of its asymmetric nature.
Referring to FIG. 1, an exemplary design is depicted of a wafer surface 40 that is laid out in a ten block configuration to facilitate a photolithography step as mentioned previously where a photoresist layer is patterned to form openings that define a shape of a main pole layer. There is a plurality of devices that will be formed within each block and each has a lengthwise dimension for the pole layer (from pole tip to back end) that is aligned parallel to the wafer flat. Note that the ten blocks are labeled A-H, J, and K. K-block is located next to the wafer flat 40f and has a lengthwise dimension “s” along the y-axis and parallel to the flat, and a widthwise dimension “w” along the x-axis direction and perpendicular to the flat. The blocks are essentially rectangles wherein J-block is formed next to an opposite side of the wafer with respect to the wafer flat, and A-H blocks are formed in two columns with four rows each between K-block and J-block. In this design, all blocks have a lengthwise dimension that is parallel to the wafer flat 40f. Half of the blocks are in an upper section of the wafer above midpoint M and half of the blocks are in the lower section of the wafer below the midpoint.
Referring to FIG. 2, within wafer uniformity is illustrated for a typical wafer after the electroplating and CMP steps. Region 1 has a main pole layer thickness that is near the mean value for the entire wafer while Region 2 has a thickness greater than the mean value. Region 3 that falls within K-block has a main pole thickness that is less than the mean value for the wafer. A low K-block thickness is not desired since it will negatively affect the EWAC (erase writer width under AC conditions) sigma for the magnetic recording heads on the wafer. Although a relatively uniform main pole layer thickness is achieved after the electroplating step, it is believed that asymmetry caused by the wafer flat along with a faster CMP removal rate near the wafer edge both contribute to the low K-block thickness issue following the polish step. Although the faster CMP removal rate at the wafer edge can be resolved by adjusting the retaining ring pressure of the wafer carrier during the CMP process, this modification still does not eliminate the K-block thickness issue. Further improvement is necessary to realize a higher degree of within wafer uniformity for main pole layer thickness such that essentially all of the devices on the wafer perform to a certain specification.
Another approach to overcome the low K-block thickness issue is to plate a thicker main pole layer in the k-block in order to compensate for a greater thinning rate in that region during the CMP step. However, it is very difficult to produce the desired plating thickness profile by using a conventional thief current adjustment method that involves a thief plate ring (auxiliary cathode) around the wafer during the plating process. Any localized thief current adjustment to the block of interest will also affect plating thickness in the remaining blocks. Thus, there is no available means to selectively plate a higher main pole layer thickness in certain regions of a wafer without affecting thickness in other regions. An improved electroplating method is desired that enables a thicker main pole layer to be formed in selected regions of a wafer while maintaining other magnetic properties in the electroplated layer.